Homepage of Michiel Soer

Postdoctoral researchers

Namedr. ir. M.C.M. Soer (Michiel) Soer, dr. ir. M.C.M.  (Michiel)
E-mail M.C.M.Soer@utwente.nl
DepartmentEEMCS / Electrical Engineering
AddressCarré, 2728
 P.O. Box 217
 7500 AE Enschede
 The Netherlands
Phone+31 53 489 4831
Secretary+31 53 489 2644
Fax+31 53 489 1034


Reconfigurable Phased Arrays

Duration: Jan 2012  -  Mar 2014

Project description:

The analog domain is one of the key challenges for reconfigurable front-ends, as reconfiguration in this domain traditionally encounters most problems. The (electronic) analog front-end is defined as all analog functionality which is located in-between the signal to-be-processed or -transmitted and the digital processing core. As such, it includes receivers, and transmitters, but also the antenna sub-system.

In reconfigurable systems all elements should support the required functionality. This also applies to the receiver part. Existing receiver technologies do not support this system requirement sufficiently. In all electromagnetic sensors and communication systems, there is a receiver part. The receiver will filter and amplify the wanted RF signals out of the whole spectrum of signals received by the antenna. The signal is processed (demodulated and/or decoded) to get access to the information contained in the signal. The unwanted signals, which can be a million times stronger than the wanted signal, have to be filtered out and the wanted signal has to be amplified and clearly processed without distortion. Up to now receiver equipment is designed in a dedicated way and is fully tuned to the application. Current and future innovations in the field of high-speed ADC’s, wideband linearization techniques and digital processing will bring new, more universal receiver building blocks paving the way for reconfigurable receiver blocks serving all kind of functions.


This project is part of the government funded STARS project: htttp://www.starsproject.nl



CMOS Beamforming Techniques

Duration: Sep 2007 - Dec 2011

Project description:

Satellite receivers with a dish antenna receive signals that fall within the so-called “beam” of the antenna. Every antenna has a characteristic "beam pattern", which is determined by the mechanical construction of the dish antenna. When using an array of antenna elements, the beam-pattern can also be defined electronically. Such beamforming can be realized via an antenna array combined with electronics,making the array direction sensitive via phase shifters or time delays. Beamforming is the basis for realizing “smart antenna’s”, which intelligently adapt their antenna beam pattern to the local environment, e.g. to maximize received signal quality and minimize interference.

Until now, beamforming is mainly applied in military applications, and more recently in base stations for telecommunication. Applications in consumer electronics are scarce, despite of the many potential advantages. This is because beamforming is typically implemented using specialized microwave and Radio Frequency (RF) technologies with hybrid module assembly techniques, and many RF-cables and connectors, unsuitable for cost-effective mass production. For consumer electronics, a high level of integration, preferably in mainstream CMOS technology, is desired. However, CMOS technology is also increasingly important for military and high-end telecom applications, because of the large amount of digital signal processing involved in smart antennas. Thus a convergence in IC-technology for telecom, military and consumer applications can be observed, leading to the observation: "If CMOS technology can, it will". From a functionality, size and cost point of view, it would be very attractive to also realize the radio interface of a beamforming system in CMOS.

In this project we want to explore fundamental options for beamforming, aiming to find new mixed analog-digital beamforming techniques suitable for CMOS. Concretely, we propose to study techniques suitable for satellite receivers in the 10-12GHz band. This is scientifically very challenging, as virtually all known beamforming systems heavily rely on high quality RF components and on microwave structures with physical sizes related to the wavelength of the radio frequency. At 10GHz the wavelength is 3cm, making microwave component sizes too large to fit on a CMOS chip. Inductors can be realized but are not very attractive as they take large chip area and have relatively poor quality. On the other hand, recent research shows that multi-GHz samplers are becoming feasible in CMOS, while jitter in samplers is less of a problem that often thought. This might open the door to new CMOS compatible beamforming techniques, using no or only a few traditional RF components. In this project we want to explore the possibilities for such techniques, focusing on the RF and mixed analog/digital signal processing.


This project is a coorporation between the Computer Architecture for Embedded Systems (CAES) and Integrated Circuit Design (ICD)  group.

PhD. students:


PhD Assignment:

The RF Circuit Design part of the CMOS Beamforming project focuses on the circuit design of phased arrays, but also overlaps with device modeling and system design. The focus is not on antenna design, as such structures are not feasible on-chip for the RF frequencies of interest.

For electronic steering, the circuit implementation of the phase shifters or time delays in CMOS poses challenges. In traditional SiGe or GaAs implementations, these components are usually composed of passive inductor-capacitor structures. In CMOS these structures will behave poorly, due to the intrinsic low Q of on-chip inductors, and will consume a lot of expensive die area. Therefore, the quest is for CMOS-friendly phase shifters or time delays, which can be heavily integrated and are compatible with future CMOS.

Possible candidates include the vector modulator (for phase shift) and time-shifted sampling (for time delay). These are constructed largely out of active components and are expected to scale performance with the increasing MOSFET speed in new technology nodes.

GDS 3D Viewer

Advanced CMOS processing nodes feature increasingly larger metal backends. As a designer, it becomes more and more difficult to visualize the makeup of a metal stack while producing layout in a 2D tool.

Therefore, we have developed an Open Source interactive 3D tool for flying through GDS layout [B]. It is powerful enough to render complete chip layouts in real time and high Frames-Per-Second count. An integration plugin with Cadence allows one to easily start a 3D view of the layout in progress, to look at via stacks, metal parasitics, and such. Layout reviews become more intuitive because the 3D geometry is immediately apparent.


UT BEamforming Array with Multiple Slices (UTBEAMS)

A 4-element beamforming receiver occupies 0.20 mm2 in 65nm CMOS. A constant-Gm vector modulator is proposed, with the weighting transconductances at RF, followed by passive mixers for I/Q generation. This enables a low power consumption of 6.5-to-9 mW per element (out of a 1.0 V supply) in a 1.0-to-2.5 GHz RF band, while achieving a high 73 dB spurious free dynamic range in 1 MHz bandwidth [1].



UT All-passive Charge-Coupling-Enabled Phased-array Transceiver (UTACCEPT)

A 4-element phased array receiver, occupying 0.18mm2 in 65nm CMOS, draws between 65 and 168mW from a 1.2V supply, for an LO frequency between 1.5 and 5.0GHz. The input-matched, fully switched-capacitor implementation of mixers, phase shifters and element summing results in a 2dBm input-referred 1dB compression point and 72dB of spurious free dynamic range in 1MHz bandwidth [3].


UT Switching Charge Redistribution Arithmetic Phase Shifter (UTSCRAPS)

A 4-element phased array receiver, with discrete-time switched-capacitor vector modulators, occupies 0.44mm2 in 65nm CMOS while drawing 308mW from 1.2V. Approximate-sine weighting is implemented through charge-redistribution. This enables a one-to-one mapping between control settings and effective phase shifts, resulting in a 1.4° phase and 0.4dB gain error (RMS) [7].



UT LInear QUadrature  Integrated Downconverter (UTLIQUID)

We propose a direct conversion receiver with a remarkably high SFDR of 79dB in 1MHz. This is realized by optimizing a 4-phase ¼ duty-cycle passive mixer for conversion loss and noise folding, while realizing the gain via IF-amplifiers linearized by resistive negative feedback. A 65nm CMOS chip consumes 67mW, while achieving a Gain>19dB, IIP3>11dBm and NF<6.5dB over 0.2-2GHz BW [10].



Educational activities:

  • Elektronische basisschakelingen (121175) 
  • Elektronische functies (121177)
  • Elektronische Basisschakelingen en Functies (121173)

UT students are welcome to apply for a Bachelor or Master Thesis assignment in the fields of:

  • Phased array system design
  • Front-end RF circuit design

The following students have finished their projects:

  • Mark Ruiter (MSc. project): Feasibility study for a clock-controlled analog beamforming frontend
  • Frederik van den Ende (MSc. project): Interference nulling via a resistor-weighted op-amp vector modulator
  • Pieter Koster (MSc. project): High IMFDR3 switched-capacitor amplifier design in CMOS 65nm
  • Remko Struiksma (BSc.project): Feedback amplifier analysis
  • Ma Song (BSc. project): Gm-C all-pass filter design


Michiel C. M. Soer was born in Schoonhoven, The Netherlands in 1984. He received the M.Sc. degree in electrical engineering and Ph.D. degree from the University of Twente, Enschede, The Netherlands, in 2007 and 2012, respectively. He is currently a post-doctoral researcher in the IC-Design Group at the University of Twente. His research interests include mixers, discrete-time systems and phased arrays in CMOS.


[1] M.C.M. Soer, E.A.M. Klumperink, B. Nauta, F.E. van Vliet, "A 1.0-to-2.5GHz Beamforming Receiver with Constant-Gm Vector Modulator Consuming < 9mW per Antenna Element in 65nm CMOS",  IEEE Solid-State Circuits Conference, Digest of Technical Papers, pp. 66-67, Feb 2014.

[2] F.E. van Vliet, E.A.M. Klumperink, M.C.M. Soer, S.K. Garakoui, A. de Boer, A.P. de Hek, W. de Heij, B. Nauta, "Advances in Silicon Phased-Array Receiver IC's", IEEE International Microwave Symposium, Digest of Technical Papers, Jun. 2012.

[3] M.C.M. Soer, E.A.M. Klumperink, B. Nauta, F.E. van Vliet, "A 1.5-to-5.0GHz Input-Matched +2dBm P1dB All-Passive Switched-Capacitor Beamforming Receiver Front-End in 65nm CMOS",  IEEE Solid-State Circuits Conference, Digest of Technical Papers, pp. 174-175, Feb 2012.

[4] M.S. Oude Alink, E.A.M. Klumperink, A.B.J. Kokkeler, M.C.M. Soer, G.J.M. Smit, B. Nauta, "A CMOS-Compatible Spectrum Analyzer for Cognitive  Radio Exploiting Crosscorrelation to Improve Noise and Linearity Performance",  IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, num. 3,  pp. 479-492, Mar. 2012.

[5] M.C.M. Soer, E.A.M. Klumperink, B. Nauta, F.E. van Vliet, "Spatial Interferer Rejection in a 4-Element Beamforming Receiver Frontend with a Switched-Capacitor Vector Modulator", IEEE Journal of Solid-State Circuits, vol.46, no.12, pp.2933-2942, Dec. 2011.

[6] A. Ghaffari, E.A.M. Klumperink, M.C.M. Soer, B. Nauta, "Tunable High-Q N-Path Band-Pass Filters: Modeling and Verification", IEEE Journal of Solid-State Circuits, vol. 46, num. 5, pp. 998, May 2011.

[7] M.C.M. Soer, E.A.M. Klumperink, B. Nauta, F.E. van Vliet, "A 1.0-to-4.0GHz 65nm CMOS Four-Element Beamforming Receiver Using a Switched-Capacitor Vector Modulator with Approximate Sine Weighting via Charge Redistribution", IEEE Solid-State Circuits Conference, Digest of Technical Papers, pp. 64-65, Feb 2011.

[8] M.S. Oude Alink, E.A.M. Klumperink, M.C.M. Soer, A.B.J. Kokkeler, B. Nauta, "A 50MHz-to-1.5GHz Cross-Correlation CMOS Spectrum Analyzer for Cognitive Radio with 89dB SFDR in 1MHz RBW", Proc. 4th IEEE Symposium on New Frontiers in Dynamic Spectrum Access Networks, Singapore, Apr. 2010.

[9] M.C.M. Soer, E.A.M. Klumperink, PT de Boer, F.E. van Vliet, B. Nauta, "Unified Frequency Domain Analysis of Switched-RC Passive Mixers and Samplers", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, num. 10,  pp. 2618-2631, Oct. 2010.

[10] M.C.M. Soer, E.A.M. Klumperink, Z. Ru, F.E. van Vliet, B. Nauta, "A 0.2-to-2.0GHz 65nm CMOS Receiver Without LNA Achieving >11dBm IIP3 and <6.5dB NF", IEEE Solid-State Circuits Conference, Digest of Technical Papers, pp. 222-223, Feb 2009.


[A] M.C.M. Soer, "Spatial Interference Rejection in Multi-Antenna CMOS Radio Receivers", RFIC Workshop, Jun. 2013.

[B] M.C.M. Soer, J. Velner, GDS3D, Available: http://sourceforge.net/projects/gds3d/.

[C] M.C.M. Soer, "Switched-RC Beamforming Receivers in Advanced CMOS", PhD Thesis, Nov. 2012.