People

Homepage of Sander Gierkink

Scientific Staff

Namedr. ir. S.L.J. Gierkink (Sander) Gierkink, dr. ir. S.L.J.  (Sander)
E-mail s.l.j.gierkink@utwente.nl
DepartmentElectrical Engineering
AddressCarré, 2005
 P.O. Box 217
 7500 AE Enschede
 The Netherlands
Phone+31 53 489 4021
Secretary+31 53 489 4831
 
 

BIOGRAPHY

Sander Gierkink received the M.Sc. (cum laude) and Ph.D. degrees in Electrical Engineering from the University of Twente, The Netherlands, in 1994 and 1999 respectively. His Ph.D. topic was on jitter and control linearity of relaxation oscillators.

In 1999 he joined Bell Laboratories, Lucent Technologies, Murray Hill, NJ. In the Communications Circuits Research department his focus was mainly on LC oscillator design for 802.11 WLAN. He continued to work for Agere Systems after it was spun off from Lucent.

In 2004 he joined Globespan Virata, Redbank, NJ, where he worked on topics like phase- and delay locked loops and ADSL linedriver  design.

In 2008 he joined Axiom IC, Enschede, The Netherlands, which was later acquired by Teledyne Dalsa in 2013. Currently he works on the design of read-out ICs for uncooled TEC-less infrared micro-bolometer cameras.

Sander Gierkink received the 1999 Else Kooi Award for his Ph.D. research, the 1998 Young Scientist Award and the 2003 Best Paper Award, both of the European Solid-State Circuits Conference, and the 2007 Best Regular Paper Award of the IEEE Custom Integrated Circuits Conference.

PhD thesis: Control linearity and jitter of relaxation oscillators

EDUCATION ACTIVITIES

Integrated Circuits/Systems for Mixed Signals (191210870)

SELECTED PUBLICATIONS

[1]     C. Mensink, E. van Tuijl, S. Gierkink, F. Mostert, R. Van der Zee, “A High-Efficiency 4x45W Car Audio Amplifier using Load Current Sharing”, Proc. of the 2010 IEEE Symposium on VLSI Circuits, June 2010.

[2]     S.L.J. Gierkink, “A 1V 15.6mW 1-2GHz -119dBc/Hz @ 200kHz clock multiplying DLL”, Proc. of the 2008 CICC, Sept. 2008.

[3]     S.L.J. Gierkink, “An 800MHz -122dBc/Hz @ 200kHz Clock Multiplier based on a Combination of PLL and recirculating DLL”, Proc. of  the  2008 ISSCC, Feb. 2008, pp. 454-455.

[4]     S.L.J. Gierkink, “A 2.5 Gb/s Run-Length-Tolerant Burst-Mode CDR Based on a 1/8th-Rate Dual Pulse Ring Oscillator”, IEEE Journal of Solid-State Circuits, Vol. 43, No. 8, Aug. 2008, pp. 1763-1771.

[5]     S.L.J. Gierkink, D. Li, R.C. Frye, V. Boccuzzi, “A 3.5GHz PLL for fast low-IF/zero-IF LO switching in an 802.11 transceiver”, IEEE Journal of Solid-State Circuits, Vol. 40, No. 9, Sept. 2005, pp. 1909-1921.

[6]     A.P. van der Wel, S.L.J. Gierkink, R.C. Frye, V. Boccuzzi, B. Nauta, “A Robust 43-GHz VCO in CMOS for OC-768 SONET Applications”, IEEE Journal of Solid-State Circuits, Vol. 39, No. 7, July 2004, pp. 1159-1163.

[7]     S.L.J. Gierkink, R.C. Frye, V. Boccuzzi, “Differentially “bathtub”-tuned CMOS VCO using inductively coupled varactors”, Proc. of the 2003 European Solid-State Circuits Conference, September 2003, pp. 501-504.

[8]     S.L.J. Gierkink, S. Levantino, R.C. Frye, C. Samori, V. Boccuzzi, “A Low-Phase-Noise 5GHz Quadrature CMOS VCO using Superharmonic Coupling”, IEEE Journal of Solid-State Circuits, Vol. 38, No. 7, July 2003, pp. 1148 –1154.

[9]     S. Levantino, C. Samori, A. Bonfanti, S.L.J. Gierkink, A.L. Lacaita, V. Boccuzzi, “Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion”, IEEE Journal of Solid-State Circuits, Vol. 37, No. 8, Aug. 2002, pp. 1003 –1011.

[10]   S.L.J. Gierkink, E. van Tuijl, “A coupled sawtooth oscillator combining low jitter with high control linearity”, IEEE Journal of Solid-State Circuits, Vol. 37, No. 6, June 2002, pp. 702 –710.

[11]   S.L.J. Gierkink, E.A.M. Klumperink, A.P. van der Wel, G. Hoogzaad, A.J.M. van Tuijl, B. Nauta,  “Intrinsic 1/f Device Noise Reduction and its Effect on Phase Noise in CMOS Ring Oscillators”, IEEE Journal of Solid-State Circuits, Vol. 34, No. 7, July 1999, pp. 1022 –1025.

[12]   E.A.M. Klumperink, S.L.J. Gierkink, A.P. van der Wel, B. Nauta, “Reducing MOSFET 1/f noise and power consumption by switched biasing”, IEEE Journal of Solid-State Circuits, Vol. 35, No. 7, July 2000, pp. 994 –1001.

[13]   A.P. van der Wel, E.A.M. Klumperink, S.L.J. Gierkink, R.F. Wassenaar, H. Wallinga, “MOSFET 1/f noise measurement under switched bias conditions”, IEEE Electron Device Letters, Vol. 21, No. 1, January 2000, pp. 43 –46.