Homepage of Claudia Palattella
PhD. students ( / AIO )
|Name||C. Palattella, MSc (Claudia)|
|Department||EEMCS / Electrical Engineering|
|P.O. Box 217|
|7500 AE Enschede|
|Phone||+31 53 489 5191|
|Secretary||+31 53 489 4831|
Hybrid Mixed Analog/Digital PLLs in 28nm FDSOI CMOS Technology
My research within the ICD group refers to the European Project Places2Be (“Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe”) . This project aims to support the deployment of a FD-SOI pilot line at 28nm and the subsequent node, as well as a dual source that will enable volume manufacturing in Europe.
FD-SOI is a low-power, high-performance next-generation alternative to conventional (“bulk”) silicon and FinFET technologies. FD-SOI stands for “Fully-Depleted Silicon-On-Insulator.” This technology improves the electrostatic control of the transistor channel, improving transistor performance and power efficiency.
My task is to investigate the possibilities of FD-SOI technology in the context of frequency synthesis, in order to design high-performance PLLs, suitable for N-path filters, that can improve the state-of-the-art, in terms of phase noise and power consumption.